Re: [PATCH 1/5] aspeed/i2c: Add support for pool buffer transfers

2019-10-16 Thread Jae Hyun Yoo
On 10/16/2019 1:50 AM, Cédric Le Goater wrote: The Aspeed I2C controller can operate in different transfer modes : - Byte Buffer mode, using a dedicated register to transfer a byte. This is what the model supports today. - Pool Buffer mode, using an internal SRAM to transfer

Re: [PATCH 1/5] aspeed/i2c: Add support for pool buffer transfers

2019-10-16 Thread Joel Stanley
On Wed, 16 Oct 2019 at 08:50, Cédric Le Goater wrote: > > The Aspeed I2C controller can operate in different transfer modes : > > - Byte Buffer mode, using a dedicated register to transfer a > byte. This is what the model supports today. > > - Pool Buffer mode, using an internal SRAM to

[PATCH 1/5] aspeed/i2c: Add support for pool buffer transfers

2019-10-16 Thread Cédric Le Goater
The Aspeed I2C controller can operate in different transfer modes : - Byte Buffer mode, using a dedicated register to transfer a byte. This is what the model supports today. - Pool Buffer mode, using an internal SRAM to transfer multiple bytes in the same command sequence. Each SoC