TheadVector unit-stride load instructions diff from RVV1.0 in the following
points:
1. Different mask reg layout.
2. Different vector reg element width.
3. Different tail/masked elements process policy.
4. Different check function.
The detials of the difference are the same as strided load instruction, as
unit-stride is the special case of strided operations.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com>
---
target/riscv/helper.h | 44 ++++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 84 ++++++++++++++++--
target/riscv/xtheadvector_helper.c | 86 +++++++++++++++++++
3 files changed, 207 insertions(+), 7 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index bfd6bd9b13..f2fa8425b3 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1317,3 +1317,47 @@ DEF_HELPER_6(th_vsse_v_b, void, ptr, ptr, tl, tl, env,
i32)
DEF_HELPER_6(th_vsse_v_h, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(th_vsse_v_w, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(th_vsse_v_d, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlb_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlh_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlh_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlh_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlh_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlh_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlh_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlw_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlw_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlw_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlw_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_b_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vle_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_b_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlbu_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlhu_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlhu_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlhu_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlhu_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlhu_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlhu_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlwu_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlwu_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlwu_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vlwu_v_d_mask, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 48004bf0d6..eb910acf40 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -321,19 +321,89 @@ GEN_TH_TRANS(th_vssh_v, 1, rnfvm, st_stride_op_th,
st_stride_check_th)
GEN_TH_TRANS(th_vssw_v, 2, rnfvm, st_stride_op_th, st_stride_check_th)
GEN_TH_TRANS(th_vsse_v, 3, rnfvm, st_stride_op_th, st_stride_check_th)
+/*
+ * unit stride load and store
+ */
+
+#define gen_helper_ldst_us_th gen_helper_ldst_us
+
+/*
+ * This function is almost the copy of ld_us_op, except:
+ * 1) different data encoding
+ * 2) XTheadVector has more insns to handle zero/sign-extended.
+ */
+static bool ld_us_op_th(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us_th *fn;
+ static gen_helper_ldst_us_th * const fns[2][7][4] = {
+ /* masked unit stride load */
+ { { gen_helper_th_vlb_v_b_mask, gen_helper_th_vlb_v_h_mask,
+ gen_helper_th_vlb_v_w_mask, gen_helper_th_vlb_v_d_mask },
+ { NULL, gen_helper_th_vlh_v_h_mask,
+ gen_helper_th_vlh_v_w_mask, gen_helper_th_vlh_v_d_mask },
+ { NULL, NULL,
+ gen_helper_th_vlw_v_w_mask, gen_helper_th_vlw_v_d_mask },
+ { gen_helper_th_vle_v_b_mask, gen_helper_th_vle_v_h_mask,
+ gen_helper_th_vle_v_w_mask, gen_helper_th_vle_v_d_mask },
+ { gen_helper_th_vlbu_v_b_mask, gen_helper_th_vlbu_v_h_mask,
+ gen_helper_th_vlbu_v_w_mask, gen_helper_th_vlbu_v_d_mask },
+ { NULL, gen_helper_th_vlhu_v_h_mask,
+ gen_helper_th_vlhu_v_w_mask, gen_helper_th_vlhu_v_d_mask },
+ { NULL, NULL,
+ gen_helper_th_vlwu_v_w_mask, gen_helper_th_vlwu_v_d_mask } },
+ /* unmasked unit stride load */
+ { { gen_helper_th_vlb_v_b, gen_helper_th_vlb_v_h,
+ gen_helper_th_vlb_v_w, gen_helper_th_vlb_v_d },
+ { NULL, gen_helper_th_vlh_v_h,
+ gen_helper_th_vlh_v_w, gen_helper_th_vlh_v_d },
+ { NULL, NULL,
+ gen_helper_th_vlw_v_w, gen_helper_th_vlw_v_d },
+ { gen_helper_th_vle_v_b, gen_helper_th_vle_v_h,
+ gen_helper_th_vle_v_w, gen_helper_th_vle_v_d },
+ { gen_helper_th_vlbu_v_b, gen_helper_th_vlbu_v_h,
+ gen_helper_th_vlbu_v_w, gen_helper_th_vlbu_v_d },
+ { NULL, gen_helper_th_vlhu_v_h,
+ gen_helper_th_vlhu_v_w, gen_helper_th_vlhu_v_d },
+ { NULL, NULL,
+ gen_helper_th_vlwu_v_w, gen_helper_th_vlwu_v_d } }
+ };
+
+ fn = fns[a->vm][seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm);
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA_TH, NF, a->nf);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
+}
+
+static bool ld_us_check_th(DisasContext *s, arg_r2nfvm* a)
+{
+ return (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_overlap_mask(s, a->rd, a->vm, false) &&
+ th_check_reg(s, a->rd, false) &&
+ th_check_nf(s, a->rd, a->nf));
+}
+
+GEN_TH_TRANS(th_vlb_v, 0, r2nfvm, ld_us_op_th, ld_us_check_th)
+GEN_TH_TRANS(th_vlh_v, 1, r2nfvm, ld_us_op_th, ld_us_check_th)
+GEN_TH_TRANS(th_vlw_v, 2, r2nfvm, ld_us_op_th, ld_us_check_th)
+GEN_TH_TRANS(th_vle_v, 3, r2nfvm, ld_us_op_th, ld_us_check_th)
+GEN_TH_TRANS(th_vlbu_v, 4, r2nfvm, ld_us_op_th, ld_us_check_th)
+GEN_TH_TRANS(th_vlhu_v, 5, r2nfvm, ld_us_op_th, ld_us_check_th)
+GEN_TH_TRANS(th_vlwu_v, 6, r2nfvm, ld_us_op_th, ld_us_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vlb_v)
-TH_TRANS_STUB(th_vlh_v)
-TH_TRANS_STUB(th_vlw_v)
-TH_TRANS_STUB(th_vle_v)
-TH_TRANS_STUB(th_vlbu_v)
-TH_TRANS_STUB(th_vlhu_v)
-TH_TRANS_STUB(th_vlwu_v)
TH_TRANS_STUB(th_vlbff_v)
TH_TRANS_STUB(th_vlhff_v)
TH_TRANS_STUB(th_vlwff_v)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index 17de312f0a..7566ab8e31 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -319,3 +319,89 @@ GEN_TH_ST_STRIDE(th_vsse_v_b, int8_t, int8_t, ste_b)
GEN_TH_ST_STRIDE(th_vsse_v_h, int16_t, int16_t, ste_h)
GEN_TH_ST_STRIDE(th_vsse_v_w, int32_t, int32_t, ste_w)
GEN_TH_ST_STRIDE(th_vsse_v_d, int64_t, int64_t, ste_d)
+
+/*
+ * unit-stride: access elements stored contiguously in memory
+ */
+
+/*
+ * unmasked unit-stride load and store operation
+ *
+ * This function is almost the copy of vext_ldst_us, except:
+ * 1) different mask layout
+ * 2) different data encoding
+ * 3) different the tail elements process policy
+ */
+static void
+th_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+ th_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
+ uint32_t esz, uint32_t msz, uintptr_t ra)
+{
+ uint32_t i, k;
+ uint32_t nf = th_nf(desc);
+ uint32_t vlmax = th_maxsz(desc) / esz;
+
+ VSTART_CHECK_EARLY_EXIT(env);
+
+ /* load bytes from guest memory */
+ for (i = env->vstart; i < env->vl; env->vstart = ++i) {
+ k = 0;
+ while (k < nf) {
+ target_ulong addr = base + (i * nf + k) * msz;
+ ldst_elem(env, adjust_addr(env, addr), i + k * vlmax, vd, ra);
+ k++;
+ }
+ }
+ env->vstart = 0;
+ /* clear tail elements */
+ if (clear_elem) {
+ for (k = 0; k < nf; k++) {
+ clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
+ }
+ }
+}
+
+/*
+ * masked unit-stride load and store operation will be a special case of
stride,
+ * stride = NF * sizeof (MTYPE)
+ *
+ * similar to GEN_GEN_VEXT_LD_US, change the function
+ */
+#define GEN_TH_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t stride = th_nf(desc) * sizeof(MTYPE); \
+ th_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
+ CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
+} \
+ \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ th_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
+ sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
+}
+
+GEN_TH_LD_US(th_vlb_v_b, int8_t, int8_t, ldb_b, clearb_th)
+GEN_TH_LD_US(th_vlb_v_h, int8_t, int16_t, ldb_h, clearh_th)
+GEN_TH_LD_US(th_vlb_v_w, int8_t, int32_t, ldb_w, clearl_th)
+GEN_TH_LD_US(th_vlb_v_d, int8_t, int64_t, ldb_d, clearq_th)
+GEN_TH_LD_US(th_vlh_v_h, int16_t, int16_t, ldh_h, clearh_th)
+GEN_TH_LD_US(th_vlh_v_w, int16_t, int32_t, ldh_w, clearl_th)
+GEN_TH_LD_US(th_vlh_v_d, int16_t, int64_t, ldh_d, clearq_th)
+GEN_TH_LD_US(th_vlw_v_w, int32_t, int32_t, ldw_w, clearl_th)
+GEN_TH_LD_US(th_vlw_v_d, int32_t, int64_t, ldw_d, clearq_th)
+GEN_TH_LD_US(th_vle_v_b, int8_t, int8_t, lde_b, clearb_th)
+GEN_TH_LD_US(th_vle_v_h, int16_t, int16_t, lde_h, clearh_th)
+GEN_TH_LD_US(th_vle_v_w, int32_t, int32_t, lde_w, clearl_th)
+GEN_TH_LD_US(th_vle_v_d, int64_t, int64_t, lde_d, clearq_th)
+GEN_TH_LD_US(th_vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb_th)
+GEN_TH_LD_US(th_vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh_th)
+GEN_TH_LD_US(th_vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl_th)
+GEN_TH_LD_US(th_vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq_th)
+GEN_TH_LD_US(th_vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh_th)
+GEN_TH_LD_US(th_vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl_th)
+GEN_TH_LD_US(th_vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq_th)
+GEN_TH_LD_US(th_vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl_th)
+GEN_TH_LD_US(th_vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq_th)
--
2.44.0
