Re: [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit

2020-02-11 Thread Philippe Mathieu-Daudé
On 2/11/20 6:37 PM, Peter Maydell wrote: The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC==0 by software is deprecated). We were implementing it incorrectly as read-only a

Re: [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit

2020-02-11 Thread Richard Henderson
On 2/11/20 9:37 AM, Peter Maydell wrote: > The LC bit in the PMCR_EL0 register is supposed to be: > * read/write > * RES1 on an AArch64-only implementation > * an architecturally UNKNOWN value on reset > (and use of LC==0 by software is deprecated). > > We were implementing it incorrectly as re

[PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit

2020-02-11 Thread Peter Maydell
The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC==0 by software is deprecated). We were implementing it incorrectly as read-only always zero, though we do have all the code nee