Re: [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs

2020-08-21 Thread Alistair Francis
On Fri, Aug 14, 2020 at 9:51 AM Bin Meng wrote: > > From: Bin Meng > > Microchip PolarFire SoC integrates 2 Candence GEMs to provide > IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. > > On the Icicle Kit board, GEM0 connects to a PHY at address 8 while > GEM1 connects to a PHY

[PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs

2020-08-14 Thread Bin Meng
From: Bin Meng Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1