Re: [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers

2020-08-21 Thread Alistair Francis
On Fri, Aug 14, 2020 at 9:53 AM Bin Meng wrote: > > From: Bin Meng > > Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems > enough to create unimplemented devices to cover their register > spaces at this point. > > With this commit, QEMU can boot to U-Boot (2nd stage bootloader) > a

[PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers

2020-08-14 Thread Bin Meng
From: Bin Meng Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (