On 6/28/21 6:58 AM, Peter Maydell wrote:
+ LSLL_rr1110101 0010 1 ... 0 ... 1 1101 @mve_shl_rr
+ ASRL_rr1110101 0010 1 ... 0 ... 1 0010 1101 @mve_shl_rr
+ UQRSHLL64_rr 1110101 0010 1 ... 1 ... 1 1101 @mve_shl_rr
+ SQRSHRL64_rr 1110101 0010
Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.
Like the long-shifts-by-immediate, these encodings sit in the s
