Add bitwise logical instructions by resuing macros define before,
Therefore, the difference depending on the macros which commited
in other patchs.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com>
---
target/riscv/helper.h | 25 +++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 20 ++++----
target/riscv/xtheadvector_helper.c | 51 +++++++++++++++++++
3 files changed, 87 insertions(+), 9 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 25fb8f81c7..6599b2f2f5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1575,3 +1575,28 @@ DEF_HELPER_6(th_vmsbc_vxm_b, void, ptr, ptr, tl, ptr,
env, i32)
DEF_HELPER_6(th_vmsbc_vxm_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vmsbc_vxm_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vmsbc_vxm_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vand_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vand_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vand_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vand_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vor_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vor_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vor_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vor_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vand_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vand_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vand_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vand_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vor_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vor_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vor_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vor_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vxor_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index a9e20a6dcb..2b7b2cfe20 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1314,21 +1314,23 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
GEN_OPIVI_TRANS_TH(th_vadc_vim, IMM_SX, th_vadc_vxm, opivx_vadc_check_th)
GEN_OPIVI_TRANS_TH(th_vmadc_vim, IMM_SX, th_vmadc_vxm, opivx_vmadc_check_th)
+/* Vector Bitwise Logical Instructions */
+GEN_OPIVV_GVEC_TRANS_TH(th_vand_vv, and)
+GEN_OPIVV_GVEC_TRANS_TH(th_vor_vv, or)
+GEN_OPIVV_GVEC_TRANS_TH(th_vxor_vv, xor)
+GEN_OPIVX_GVEC_TRANS_TH(th_vand_vx, ands)
+GEN_OPIVX_GVEC_TRANS_TH(th_vor_vx, ors)
+GEN_OPIVX_GVEC_TRANS_TH(th_vxor_vx, xors)
+GEN_OPIVI_GVEC_TRANS_TH(th_vand_vi, IMM_SX, th_vand_vx, andi)
+GEN_OPIVI_GVEC_TRANS_TH(th_vor_vi, IMM_SX, th_vor_vx, ori)
+GEN_OPIVI_GVEC_TRANS_TH(th_vxor_vi, IMM_SX, th_vxor_vx, xori)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vand_vv)
-TH_TRANS_STUB(th_vand_vx)
-TH_TRANS_STUB(th_vand_vi)
-TH_TRANS_STUB(th_vor_vv)
-TH_TRANS_STUB(th_vor_vx)
-TH_TRANS_STUB(th_vor_vi)
-TH_TRANS_STUB(th_vxor_vv)
-TH_TRANS_STUB(th_vxor_vx)
-TH_TRANS_STUB(th_vxor_vi)
TH_TRANS_STUB(th_vsll_vv)
TH_TRANS_STUB(th_vsll_vx)
TH_TRANS_STUB(th_vsll_vi)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index e5058d09f6..85fa69dd82 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -1223,3 +1223,54 @@ GEN_TH_VMADC_VXM(th_vmsbc_vxm_b, uint8_t, H1, TH_MSBC)
GEN_TH_VMADC_VXM(th_vmsbc_vxm_h, uint16_t, H2, TH_MSBC)
GEN_TH_VMADC_VXM(th_vmsbc_vxm_w, uint32_t, H4, TH_MSBC)
GEN_TH_VMADC_VXM(th_vmsbc_vxm_d, uint64_t, H8, TH_MSBC)
+
+/* Vector Bitwise Logical Instructions */
+THCALL(TH_OPIVV2, th_vand_vv_b, OP_SSS_B, H1, H1, H1, TH_AND)
+THCALL(TH_OPIVV2, th_vand_vv_h, OP_SSS_H, H2, H2, H2, TH_AND)
+THCALL(TH_OPIVV2, th_vand_vv_w, OP_SSS_W, H4, H4, H4, TH_AND)
+THCALL(TH_OPIVV2, th_vand_vv_d, OP_SSS_D, H8, H8, H8, TH_AND)
+THCALL(TH_OPIVV2, th_vor_vv_b, OP_SSS_B, H1, H1, H1, TH_OR)
+THCALL(TH_OPIVV2, th_vor_vv_h, OP_SSS_H, H2, H2, H2, TH_OR)
+THCALL(TH_OPIVV2, th_vor_vv_w, OP_SSS_W, H4, H4, H4, TH_OR)
+THCALL(TH_OPIVV2, th_vor_vv_d, OP_SSS_D, H8, H8, H8, TH_OR)
+THCALL(TH_OPIVV2, th_vxor_vv_b, OP_SSS_B, H1, H1, H1, TH_XOR)
+THCALL(TH_OPIVV2, th_vxor_vv_h, OP_SSS_H, H2, H2, H2, TH_XOR)
+THCALL(TH_OPIVV2, th_vxor_vv_w, OP_SSS_W, H4, H4, H4, TH_XOR)
+THCALL(TH_OPIVV2, th_vxor_vv_d, OP_SSS_D, H8, H8, H8, TH_XOR)
+GEN_TH_VV(th_vand_vv_b, 1, 1, clearb_th)
+GEN_TH_VV(th_vand_vv_h, 2, 2, clearh_th)
+GEN_TH_VV(th_vand_vv_w, 4, 4, clearl_th)
+GEN_TH_VV(th_vand_vv_d, 8, 8, clearq_th)
+GEN_TH_VV(th_vor_vv_b, 1, 1, clearb_th)
+GEN_TH_VV(th_vor_vv_h, 2, 2, clearh_th)
+GEN_TH_VV(th_vor_vv_w, 4, 4, clearl_th)
+GEN_TH_VV(th_vor_vv_d, 8, 8, clearq_th)
+GEN_TH_VV(th_vxor_vv_b, 1, 1, clearb_th)
+GEN_TH_VV(th_vxor_vv_h, 2, 2, clearh_th)
+GEN_TH_VV(th_vxor_vv_w, 4, 4, clearl_th)
+GEN_TH_VV(th_vxor_vv_d, 8, 8, clearq_th)
+
+THCALL(TH_OPIVX2, th_vand_vx_b, OP_SSS_B, H1, H1, TH_AND)
+THCALL(TH_OPIVX2, th_vand_vx_h, OP_SSS_H, H2, H2, TH_AND)
+THCALL(TH_OPIVX2, th_vand_vx_w, OP_SSS_W, H4, H4, TH_AND)
+THCALL(TH_OPIVX2, th_vand_vx_d, OP_SSS_D, H8, H8, TH_AND)
+THCALL(TH_OPIVX2, th_vor_vx_b, OP_SSS_B, H1, H1, TH_OR)
+THCALL(TH_OPIVX2, th_vor_vx_h, OP_SSS_H, H2, H2, TH_OR)
+THCALL(TH_OPIVX2, th_vor_vx_w, OP_SSS_W, H4, H4, TH_OR)
+THCALL(TH_OPIVX2, th_vor_vx_d, OP_SSS_D, H8, H8, TH_OR)
+THCALL(TH_OPIVX2, th_vxor_vx_b, OP_SSS_B, H1, H1, TH_XOR)
+THCALL(TH_OPIVX2, th_vxor_vx_h, OP_SSS_H, H2, H2, TH_XOR)
+THCALL(TH_OPIVX2, th_vxor_vx_w, OP_SSS_W, H4, H4, TH_XOR)
+THCALL(TH_OPIVX2, th_vxor_vx_d, OP_SSS_D, H8, H8, TH_XOR)
+GEN_TH_VX(th_vand_vx_b, 1, 1, clearb_th)
+GEN_TH_VX(th_vand_vx_h, 2, 2, clearh_th)
+GEN_TH_VX(th_vand_vx_w, 4, 4, clearl_th)
+GEN_TH_VX(th_vand_vx_d, 8, 8, clearq_th)
+GEN_TH_VX(th_vor_vx_b, 1, 1, clearb_th)
+GEN_TH_VX(th_vor_vx_h, 2, 2, clearh_th)
+GEN_TH_VX(th_vor_vx_w, 4, 4, clearl_th)
+GEN_TH_VX(th_vor_vx_d, 8, 8, clearq_th)
+GEN_TH_VX(th_vxor_vx_b, 1, 1, clearb_th)
+GEN_TH_VX(th_vxor_vx_h, 2, 2, clearh_th)
+GEN_TH_VX(th_vxor_vx_w, 4, 4, clearl_th)
+GEN_TH_VX(th_vxor_vx_d, 8, 8, clearq_th)
--
2.44.0
