Re: [PATCH 2/2] target/riscv: Raise an exception when sdtrig is turned off

On Wed, Jan 10, 2024 at 2:03 PM Himanshu Chauhan wrote: > > When sdtrig is turned off by "sdtrig=false" option, raise > and illegal instruction exception on any read/write to > sdtrig CSRs. > > Signed-off-by: Himanshu Chauhan > --- > target/riscv/csr.c | 20 > 1 file changed

[PATCH 2/2] target/riscv: Raise an exception when sdtrig is turned off

When sdtrig is turned off by "sdtrig=false" option, raise and illegal instruction exception on any read/write to sdtrig CSRs. Signed-off-by: Himanshu Chauhan --- target/riscv/csr.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c i