On 6/9/24 11:11, Chinmay Rath wrote:
The calculation of effective address in these instructions is slightly different than the
others,
for which helper function exist :
EA for these insns : EA ← (RA=0) ? 0 : GPR[RA]
EA for rest storage access insns : EA ← ((RA=0) ? 0 : GPR[RA]) + GPR[RB]
This
Hi Richard,
On 6/7/24 21:11, Richard Henderson wrote:
On 6/7/24 07:49, Chinmay Rath wrote:
+static bool do_ld_st_vl(DisasContext *ctx, arg_X *a,
+ void (*helper)(TCGv_ptr, TCGv, TCGv_ptr, TCGv))
+{
+ TCGv EA;
+ TCGv_ptr xt;
+ if (a->rt < 32) {
+ REQUIRE_
On 6/7/24 07:49, Chinmay Rath wrote:
+static bool do_ld_st_vl(DisasContext *ctx, arg_X *a,
+void (*helper)(TCGv_ptr, TCGv, TCGv_ptr, TCGv))
+{
+TCGv EA;
+TCGv_ptr xt;
+if (a->rt < 32) {
+REQUIRE_VSX(ctx);
+} else {
+REQUIRE_VECTOR(ctx);
+
Moving the following instructions to decodetree specification :
{l, st}xvl(l) : X-form
The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
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