On Mon, May 9, 2022 at 2:54 PM Alistair Francis wrote:
>
> On Thu, May 5, 2022 at 12:36 PM Anup Patel wrote:
> >
> > On Thu, May 5, 2022 at 3:21 PM Alistair Francis
> > wrote:
> > >
> > > On Fri, Apr 29, 2022 at 1:38 PM Anup Patel
> > > wrote:
> > > >
> > > > Currently, QEMU does not set
On Thu, May 5, 2022 at 12:36 PM Anup Patel wrote:
>
> On Thu, May 5, 2022 at 3:21 PM Alistair Francis wrote:
> >
> > On Fri, Apr 29, 2022 at 1:38 PM Anup Patel wrote:
> > >
> > > Currently, QEMU does not set hstatus.GVA bit for traps taken from
> > > HS-mode into HS-mode which breaks the Xvisor
On Thu, May 5, 2022 at 3:21 PM Alistair Francis wrote:
>
> On Fri, Apr 29, 2022 at 1:38 PM Anup Patel wrote:
> >
> > Currently, QEMU does not set hstatus.GVA bit for traps taken from
> > HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
> > on QEMU. This was working previously.
On Fri, Apr 29, 2022 at 1:38 PM Anup Patel wrote:
>
> Currently, QEMU does not set hstatus.GVA bit for traps taken from
> HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
> on QEMU. This was working previously.
>
> This patch updates riscv_cpu_do_interrupt() to fix the above
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
