CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on
PCI and is IO port based and hence existing cpus AML code assumes _CRS objects
would evaluate to a system resource which describes IO Port address. But on
LOONGARCH
arch CPUs control device(\\_SB.PRES) register interfa
On Thu, 20 Jul 2023 15:15:07 +0800
xianglai li wrote:
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based
> on
> PCI and is IO port based and hence existing cpus AML code assumes _CRS objects
> would evaluate to a system resource which describes IO Port address. But on
Hi, Igor Mammedov :
On 7/28/23 7:55 PM, Igor Mammedov wrote:
On Thu, 20 Jul 2023 15:15:07 +0800
xianglai li wrote:
CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on
PCI and is IO port based and hence existing cpus AML code assumes _CRS objects
would evaluate to a
