The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com>
---
target/riscv/helper.h | 33 +++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 18 +++--
target/riscv/xtheadvector_helper.c | 74 +++++++++++++++++++
3 files changed, 117 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e678dd5385..3d5ad2847e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1761,3 +1761,36 @@ DEF_HELPER_6(th_vmulhsu_vx_b, void, ptr, ptr, tl, ptr,
env, i32)
DEF_HELPER_6(th_vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vdivu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdivu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdivu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdivu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vdivu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vdivu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vdivu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vdivu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vdiv_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vremu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 15f36ba98a..a609b7faf3 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1539,20 +1539,22 @@ GEN_OPIVX_TRANS_TH(th_vmulh_vx, opivx_check_th)
GEN_OPIVX_TRANS_TH(th_vmulhu_vx, opivx_check_th)
GEN_OPIVX_TRANS_TH(th_vmulhsu_vx, opivx_check_th)
+/* Vector Integer Divide Instructions */
+GEN_OPIVV_TRANS_TH(th_vdivu_vv, opivv_check_th)
+GEN_OPIVV_TRANS_TH(th_vdiv_vv, opivv_check_th)
+GEN_OPIVV_TRANS_TH(th_vremu_vv, opivv_check_th)
+GEN_OPIVV_TRANS_TH(th_vrem_vv, opivv_check_th)
+GEN_OPIVX_TRANS_TH(th_vdivu_vx, opivx_check_th)
+GEN_OPIVX_TRANS_TH(th_vdiv_vx, opivx_check_th)
+GEN_OPIVX_TRANS_TH(th_vremu_vx, opivx_check_th)
+GEN_OPIVX_TRANS_TH(th_vrem_vx, opivx_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vdivu_vv)
-TH_TRANS_STUB(th_vdivu_vx)
-TH_TRANS_STUB(th_vdiv_vv)
-TH_TRANS_STUB(th_vdiv_vx)
-TH_TRANS_STUB(th_vremu_vv)
-TH_TRANS_STUB(th_vremu_vx)
-TH_TRANS_STUB(th_vrem_vv)
-TH_TRANS_STUB(th_vrem_vx)
TH_TRANS_STUB(th_vwmulu_vv)
TH_TRANS_STUB(th_vwmulu_vx)
TH_TRANS_STUB(th_vwmulsu_vv)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index 9d8129750c..4af66b047a 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -1678,3 +1678,77 @@ GEN_TH_VX(th_vmulhsu_vx_b, 1, 1, clearb_th)
GEN_TH_VX(th_vmulhsu_vx_h, 2, 2, clearh_th)
GEN_TH_VX(th_vmulhsu_vx_w, 4, 4, clearl_th)
GEN_TH_VX(th_vmulhsu_vx_d, 8, 8, clearq_th)
+
+/* Vector Integer Divide Instructions */
+#define TH_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
+#define TH_REMU(N, M) (unlikely(M == 0) ? N : N % M)
+#define TH_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
+ unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
+#define TH_REM(N, M) (unlikely(M == 0) ? N :\
+ unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
+
+THCALL(TH_OPIVV2, th_vdivu_vv_b, OP_UUU_B, H1, H1, H1, TH_DIVU)
+THCALL(TH_OPIVV2, th_vdivu_vv_h, OP_UUU_H, H2, H2, H2, TH_DIVU)
+THCALL(TH_OPIVV2, th_vdivu_vv_w, OP_UUU_W, H4, H4, H4, TH_DIVU)
+THCALL(TH_OPIVV2, th_vdivu_vv_d, OP_UUU_D, H8, H8, H8, TH_DIVU)
+THCALL(TH_OPIVV2, th_vdiv_vv_b, OP_SSS_B, H1, H1, H1, TH_DIV)
+THCALL(TH_OPIVV2, th_vdiv_vv_h, OP_SSS_H, H2, H2, H2, TH_DIV)
+THCALL(TH_OPIVV2, th_vdiv_vv_w, OP_SSS_W, H4, H4, H4, TH_DIV)
+THCALL(TH_OPIVV2, th_vdiv_vv_d, OP_SSS_D, H8, H8, H8, TH_DIV)
+THCALL(TH_OPIVV2, th_vremu_vv_b, OP_UUU_B, H1, H1, H1, TH_REMU)
+THCALL(TH_OPIVV2, th_vremu_vv_h, OP_UUU_H, H2, H2, H2, TH_REMU)
+THCALL(TH_OPIVV2, th_vremu_vv_w, OP_UUU_W, H4, H4, H4, TH_REMU)
+THCALL(TH_OPIVV2, th_vremu_vv_d, OP_UUU_D, H8, H8, H8, TH_REMU)
+THCALL(TH_OPIVV2, th_vrem_vv_b, OP_SSS_B, H1, H1, H1, TH_REM)
+THCALL(TH_OPIVV2, th_vrem_vv_h, OP_SSS_H, H2, H2, H2, TH_REM)
+THCALL(TH_OPIVV2, th_vrem_vv_w, OP_SSS_W, H4, H4, H4, TH_REM)
+THCALL(TH_OPIVV2, th_vrem_vv_d, OP_SSS_D, H8, H8, H8, TH_REM)
+GEN_TH_VV(th_vdivu_vv_b, 1, 1, clearb_th)
+GEN_TH_VV(th_vdivu_vv_h, 2, 2, clearh_th)
+GEN_TH_VV(th_vdivu_vv_w, 4, 4, clearl_th)
+GEN_TH_VV(th_vdivu_vv_d, 8, 8, clearq_th)
+GEN_TH_VV(th_vdiv_vv_b, 1, 1, clearb_th)
+GEN_TH_VV(th_vdiv_vv_h, 2, 2, clearh_th)
+GEN_TH_VV(th_vdiv_vv_w, 4, 4, clearl_th)
+GEN_TH_VV(th_vdiv_vv_d, 8, 8, clearq_th)
+GEN_TH_VV(th_vremu_vv_b, 1, 1, clearb_th)
+GEN_TH_VV(th_vremu_vv_h, 2, 2, clearh_th)
+GEN_TH_VV(th_vremu_vv_w, 4, 4, clearl_th)
+GEN_TH_VV(th_vremu_vv_d, 8, 8, clearq_th)
+GEN_TH_VV(th_vrem_vv_b, 1, 1, clearb_th)
+GEN_TH_VV(th_vrem_vv_h, 2, 2, clearh_th)
+GEN_TH_VV(th_vrem_vv_w, 4, 4, clearl_th)
+GEN_TH_VV(th_vrem_vv_d, 8, 8, clearq_th)
+
+THCALL(TH_OPIVX2, th_vdivu_vx_b, OP_UUU_B, H1, H1, TH_DIVU)
+THCALL(TH_OPIVX2, th_vdivu_vx_h, OP_UUU_H, H2, H2, TH_DIVU)
+THCALL(TH_OPIVX2, th_vdivu_vx_w, OP_UUU_W, H4, H4, TH_DIVU)
+THCALL(TH_OPIVX2, th_vdivu_vx_d, OP_UUU_D, H8, H8, TH_DIVU)
+THCALL(TH_OPIVX2, th_vdiv_vx_b, OP_SSS_B, H1, H1, TH_DIV)
+THCALL(TH_OPIVX2, th_vdiv_vx_h, OP_SSS_H, H2, H2, TH_DIV)
+THCALL(TH_OPIVX2, th_vdiv_vx_w, OP_SSS_W, H4, H4, TH_DIV)
+THCALL(TH_OPIVX2, th_vdiv_vx_d, OP_SSS_D, H8, H8, TH_DIV)
+THCALL(TH_OPIVX2, th_vremu_vx_b, OP_UUU_B, H1, H1, TH_REMU)
+THCALL(TH_OPIVX2, th_vremu_vx_h, OP_UUU_H, H2, H2, TH_REMU)
+THCALL(TH_OPIVX2, th_vremu_vx_w, OP_UUU_W, H4, H4, TH_REMU)
+THCALL(TH_OPIVX2, th_vremu_vx_d, OP_UUU_D, H8, H8, TH_REMU)
+THCALL(TH_OPIVX2, th_vrem_vx_b, OP_SSS_B, H1, H1, TH_REM)
+THCALL(TH_OPIVX2, th_vrem_vx_h, OP_SSS_H, H2, H2, TH_REM)
+THCALL(TH_OPIVX2, th_vrem_vx_w, OP_SSS_W, H4, H4, TH_REM)
+THCALL(TH_OPIVX2, th_vrem_vx_d, OP_SSS_D, H8, H8, TH_REM)
+GEN_TH_VX(th_vdivu_vx_b, 1, 1, clearb_th)
+GEN_TH_VX(th_vdivu_vx_h, 2, 2, clearh_th)
+GEN_TH_VX(th_vdivu_vx_w, 4, 4, clearl_th)
+GEN_TH_VX(th_vdivu_vx_d, 8, 8, clearq_th)
+GEN_TH_VX(th_vdiv_vx_b, 1, 1, clearb_th)
+GEN_TH_VX(th_vdiv_vx_h, 2, 2, clearh_th)
+GEN_TH_VX(th_vdiv_vx_w, 4, 4, clearl_th)
+GEN_TH_VX(th_vdiv_vx_d, 8, 8, clearq_th)
+GEN_TH_VX(th_vremu_vx_b, 1, 1, clearb_th)
+GEN_TH_VX(th_vremu_vx_h, 2, 2, clearh_th)
+GEN_TH_VX(th_vremu_vx_w, 4, 4, clearl_th)
+GEN_TH_VX(th_vremu_vx_d, 8, 8, clearq_th)
+GEN_TH_VX(th_vrem_vx_b, 1, 1, clearb_th)
+GEN_TH_VX(th_vrem_vx_h, 2, 2, clearh_th)
+GEN_TH_VX(th_vrem_vx_w, 4, 4, clearl_th)
+GEN_TH_VX(th_vrem_vx_d, 8, 8, clearq_th)
--
2.44.0
