Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

2021-06-15 Thread Anup Patel
On Tue, Jun 15, 2021 at 1:41 PM Alistair Francis wrote: > > On Sat, Jun 12, 2021 at 12:04 AM Anup Patel wrote: > > > > On Fri, Jun 11, 2021 at 2:16 PM Alistair Francis > > wrote: > > > > > > On Fri, Jun 11, 2021 at 3:04 PM Anup Patel wrote: > > > > > > > > On Fri, Jun 11, 2021 at 4:49 AM

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

2021-06-15 Thread Alistair Francis
On Sat, Jun 12, 2021 at 12:04 AM Anup Patel wrote: > > On Fri, Jun 11, 2021 at 2:16 PM Alistair Francis wrote: > > > > On Fri, Jun 11, 2021 at 3:04 PM Anup Patel wrote: > > > > > > On Fri, Jun 11, 2021 at 4:49 AM Alistair Francis > > > wrote: > > > > > > > > On Sat, May 15, 2021 at 12:34 AM

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

2021-06-11 Thread Anup Patel
On Fri, Jun 11, 2021 at 2:16 PM Alistair Francis wrote: > > On Fri, Jun 11, 2021 at 3:04 PM Anup Patel wrote: > > > > On Fri, Jun 11, 2021 at 4:49 AM Alistair Francis > > wrote: > > > > > > On Sat, May 15, 2021 at 12:34 AM Anup Patel wrote: > > > > > > > > We implement various AIA local

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

2021-06-11 Thread Alistair Francis
On Fri, Jun 11, 2021 at 3:04 PM Anup Patel wrote: > > On Fri, Jun 11, 2021 at 4:49 AM Alistair Francis wrote: > > > > On Sat, May 15, 2021 at 12:34 AM Anup Patel wrote: > > > > > > We implement various AIA local interrupt CSRs for M-mode, HS-mode, > > > and VS-mode. > > > > > > Signed-off-by:

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

2021-06-10 Thread Anup Patel
On Fri, Jun 11, 2021 at 4:49 AM Alistair Francis wrote: > > On Sat, May 15, 2021 at 12:34 AM Anup Patel wrote: > > > > We implement various AIA local interrupt CSRs for M-mode, HS-mode, > > and VS-mode. > > > > Signed-off-by: Anup Patel > > --- > > target/riscv/cpu.c| 27 +- > >

Re: [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

2021-06-10 Thread Alistair Francis
On Sat, May 15, 2021 at 12:34 AM Anup Patel wrote: > > We implement various AIA local interrupt CSRs for M-mode, HS-mode, > and VS-mode. > > Signed-off-by: Anup Patel > --- > target/riscv/cpu.c| 27 +- > target/riscv/cpu.h| 52 +- > target/riscv/cpu_helper.c | 245 -

[PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs

2021-05-14 Thread Anup Patel
We implement various AIA local interrupt CSRs for M-mode, HS-mode, and VS-mode. Signed-off-by: Anup Patel --- target/riscv/cpu.c| 27 +- target/riscv/cpu.h| 52 +- target/riscv/cpu_helper.c | 245 - target/riscv/csr.c| 1059