subject:"\[PATCH 3\/4\] target\/riscv\: Set the value of CSR tcontrol when trapping to M\-mode"

Re: [PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode

2024-02-16 Thread Daniel Henrique Barboza

On 2/16/24 03:13, Alvin Chang wrote: From the RISC-V debug specification, it defines the following operations for CSR tcontrol when any trap into M-mode is taken: 1. tcontrol.MPTE is set to the value of tcontrol.MTE 2. tcontrol.MTE is set to 0 This commit implements the above operations

[PATCH 3/4] target/riscv: Set the value of CSR tcontrol when trapping to M-mode

2024-02-15 Thread Alvin Chang via

>From the RISC-V debug specification, it defines the following operations for CSR tcontrol when any trap into M-mode is taken: 1. tcontrol.MPTE is set to the value of tcontrol.MTE 2. tcontrol.MTE is set to 0 This commit implements the above operations into riscv_cpu_do_interrupt().