On 2023/6/12 13:40, LIU Zhiwei wrote:
On 2023/6/12 12:35, Weiwei Li wrote:
On 2023/6/12 11:18, LIU Zhiwei wrote:
On 2023/6/12 11:16, Weiwei Li wrote:
On 2023/6/12 11:08, LIU Zhiwei wrote:
On 2023/5/29 20:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatu
On 2023/6/12 12:35, Weiwei Li wrote:
On 2023/6/12 11:18, LIU Zhiwei wrote:
On 2023/6/12 11:16, Weiwei Li wrote:
On 2023/6/12 11:08, LIU Zhiwei wrote:
On 2023/5/29 20:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Have you
On 2023/6/12 11:18, LIU Zhiwei wrote:
On 2023/6/12 11:16, Weiwei Li wrote:
On 2023/6/12 11:08, LIU Zhiwei wrote:
On 2023/5/29 20:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Have you found the CSR field specifications for
On 2023/6/12 11:16, Weiwei Li wrote:
On 2023/6/12 11:08, LIU Zhiwei wrote:
On 2023/5/29 20:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Have you found the CSR field specifications for them, especially for
GVA.
Yeah. in
On 2023/6/12 11:08, LIU Zhiwei wrote:
On 2023/5/29 20:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Have you found the CSR field specifications for them, especially for GVA.
Yeah. in the section 9.4.1 of the privilege spec:
On 2023/5/29 20:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Have you found the CSR field specifications for them, especially for GVA.
Zhiwei
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c
On Mon, May 29, 2023 at 10:18 PM Weiwei Li wrote:
>
> MPV and GVA bits are added by hypervisor extension to mstatus
> and mstatush (if MXLEN=32).
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 10 --
>
On 5/29/23 09:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c | 10 --
1 file changed, 4 insertion
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 584
