[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

2024-05-15 Thread Fea.Wang
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 2 files changed, 9 insertions(+

Re: [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

2024-05-15 Thread Fea Wang
Thank you, I will correct it in the patch v2. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:51寫道: > > On 2024/5/10 14:58, Fea.Wang wrote: > > Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in > > SMSTATEEN0 that controls access to the hedeleg. > > > > Signed-off-by: Fea.Wang

Re: [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

2024-05-12 Thread LIU Zhiwei
On 2024/5/10 14:58, Fea.Wang wrote: Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 10 ++ 2 files c

Re: [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

2024-05-11 Thread liwei
On 2024/5/10 14:58, Fea.Wang wrote: Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 10 ++ 2 files c

[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0

2024-05-10 Thread Fea.Wang
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 10 ++ 2 files changed, 11 insertions(+) diff --git a/targ