Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

It makes sense. Thank you for the explanation. Rajnesh Kanwal 於 2024年6月10日 週一 下午10:12寫道： > > Thanks Jason for your review. > > On Tue, Jun 4, 2024 at 11:14 AM Jason Chien > wrote: > > > > > > Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > > > > This commit adds support for [m|s|vs]ctrcontrol, sctrst

Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

Thanks Jason for your review. On Tue, Jun 4, 2024 at 11:14 AM Jason Chien wrote: > > > Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > > This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and > sctrdepth CSRs handling. > > Signed-off-by: Rajnesh Kanwal > --- > target/riscv/cpu.h | 5 ++

Re: [PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 159 ++

[PATCH 3/6] target/riscv: Add support for Control Transfer Records extension CSRs.

This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and sctrdepth CSRs handling. Signed-off-by: Rajnesh Kanwal --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_cfg.h | 2 + target/riscv/csr.c | 159 + 3 files changed, 166 insertions(+)