The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com>
---
target/riscv/helper.h | 16 +++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 12 ++++---
target/riscv/vector_helper.c | 6 ++--
target/riscv/vector_internals.h | 4 +++
target/riscv/xtheadvector_helper.c | 34 +++++++++++++++++++
5 files changed, 64 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 21916e9e3c..f63239676a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2029,3 +2029,19 @@ DEF_HELPER_6(th_vfwadd_wf_h, void, ptr, ptr, i64, ptr,
env, i32)
DEF_HELPER_6(th_vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(th_vfmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vfmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfmul_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(th_vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 64d7a7fb76..940b212f5e 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2008,17 +2008,19 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
GEN_OPFWF_WIDEN_TRANS_TH(th_vfwadd_wf)
GEN_OPFWF_WIDEN_TRANS_TH(th_vfwsub_wf)
+/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
+GEN_OPFVV_TRANS_TH(th_vfmul_vv, opfvv_check_th)
+GEN_OPFVV_TRANS_TH(th_vfdiv_vv, opfvv_check_th)
+GEN_OPFVF_TRANS_TH(th_vfmul_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfdiv_vf, opfvf_check_th)
+GEN_OPFVF_TRANS_TH(th_vfrdiv_vf, opfvf_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vfmul_vv)
-TH_TRANS_STUB(th_vfmul_vf)
-TH_TRANS_STUB(th_vfdiv_vv)
-TH_TRANS_STUB(th_vfdiv_vf)
-TH_TRANS_STUB(th_vfrdiv_vf)
TH_TRANS_STUB(th_vfwmul_vv)
TH_TRANS_STUB(th_vfwmul_vf)
TH_TRANS_STUB(th_vfmacc_vv)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6d0358876a..d65b32c584 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3036,17 +3036,17 @@ GEN_VEXT_VF(vfdiv_vf_h, 2)
GEN_VEXT_VF(vfdiv_vf_w, 4)
GEN_VEXT_VF(vfdiv_vf_d, 8)
-static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s)
+uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s)
{
return float16_div(b, a, s);
}
-static uint32_t float32_rdiv(uint32_t a, uint32_t b, float_status *s)
+uint32_t float32_rdiv(uint32_t a, uint32_t b, float_status *s)
{
return float32_div(b, a, s);
}
-static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s)
+uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s)
{
return float64_div(b, a, s);
}
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index 0786f5a4e1..29263c6a53 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -353,4 +353,8 @@ uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s);
uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s);
uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s);
+uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s);
+uint32_t float32_rdiv(uint32_t a, uint32_t b, float_status *s);
+uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s);
+
#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index cab489a4ae..770f36346f 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -2734,3 +2734,37 @@ THCALL(TH_OPFVF2, th_vfwsub_wf_h, WOP_WUUU_H, H4, H2,
vfwsubw16)
THCALL(TH_OPFVF2, th_vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
GEN_TH_VF(th_vfwsub_wf_h, 2, 4, clearl_th)
GEN_TH_VF(th_vfwsub_wf_w, 4, 8, clearq_th)
+
+/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
+THCALL(TH_OPFVV2, th_vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul)
+THCALL(TH_OPFVV2, th_vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul)
+THCALL(TH_OPFVV2, th_vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul)
+GEN_TH_VV_ENV(th_vfmul_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfmul_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfmul_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF2, th_vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul)
+THCALL(TH_OPFVF2, th_vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul)
+THCALL(TH_OPFVF2, th_vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul)
+GEN_TH_VF(th_vfmul_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfmul_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfmul_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVV2, th_vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div)
+THCALL(TH_OPFVV2, th_vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div)
+THCALL(TH_OPFVV2, th_vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div)
+GEN_TH_VV_ENV(th_vfdiv_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_ENV(th_vfdiv_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_ENV(th_vfdiv_vv_d, 8, 8, clearq_th)
+THCALL(TH_OPFVF2, th_vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div)
+THCALL(TH_OPFVF2, th_vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div)
+THCALL(TH_OPFVF2, th_vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div)
+GEN_TH_VF(th_vfdiv_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfdiv_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfdiv_vf_d, 8, 8, clearq_th)
+
+THCALL(TH_OPFVF2, th_vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv)
+THCALL(TH_OPFVF2, th_vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv)
+THCALL(TH_OPFVF2, th_vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
+GEN_TH_VF(th_vfrdiv_vf_h, 2, 2, clearh_th)
+GEN_TH_VF(th_vfrdiv_vf_w, 4, 4, clearl_th)
+GEN_TH_VF(th_vfrdiv_vf_d, 8, 8, clearq_th)
--
2.44.0
