On 6/7/22 02:58, Peter Maydell wrote:
@@ -3292,6 +3292,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
+FIELD(TBFLAG_A64, SVL, 24, 4)
Given that both SVE and SME start with an 'S', maybe
On Thu, 2 Jun 2022 at 23:18, Richard Henderson
wrote:
>
> We need SVL separate from VL for RDSVL at al, as well as
"et al"
> ZA storage loads and stores, which do not require PSTATE.SM.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 12
> target/arm/tran
We need SVL separate from VL for RDSVL at al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 12
target/arm/translate.h | 1 +
target/arm/helper.c| 8 +++-
target/arm/transla
