Alistair Francis writes:
>> +return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 0);
>
> How would sizeof(target_ulong) == 0 ?
Oops. This is supposed to be 8, not 0. And those look very similar on
the screen. I caught this myself a couple of weeks ago but forgot to
send out a
On Wed, Oct 28, 2020 at 12:04 PM Keith Packard via
wrote:
>
> Adapt the arm semihosting support code for RISCV. This implementation
> is based on the standard for RISC-V semihosting version 0.2 as
> documented in
>
>https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
>
>
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is
