[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be cont

Re: [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

OK, I will correct it in the patch v2. Thank you. Sincerely, Fea LIU Zhiwei 於 2024年5月13日 週一 上午10:49寫道： > > On 2024/5/10 14:58, Fea.Wang wrote: > > Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH > > and HEDELEGH for exception codes 32-47 for reserving and exception codes > >

Re: [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

On 2024/5/10 14:58, Fea.Wang wrote: Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, f

[PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be cont