The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com>
---
target/riscv/helper.h | 4 ++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 46 ++++++++++++++++++-
target/riscv/xtheadvector_helper.c | 41 +++++++++++++++++
3 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 12b5e4573a..5aa12f3719 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2116,3 +2116,7 @@ DEF_HELPER_6(th_vfwmsac_vf_h, void, ptr, ptr, i64, ptr,
env, i32)
DEF_HELPER_6(th_vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_5(th_vfsqrt_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfsqrt_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfsqrt_v_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 7220b7d607..e709444e9f 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2047,13 +2047,57 @@ GEN_OPFVF_WIDEN_TRANS_TH(th_vfwnmacc_vf)
GEN_OPFVF_WIDEN_TRANS_TH(th_vfwmsac_vf)
GEN_OPFVF_WIDEN_TRANS_TH(th_vfwnmsac_vf)
+/* Vector Floating-Point Square-Root Instruction */
+
+/*
+ * If the current SEW does not correspond to a supported IEEE floating-point
+ * type, an illegal instruction exception is raised
+ */
+static bool opfv_check_th(DisasContext *s, arg_rmr *a)
+{
+ return require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_overlap_mask(s, a->rd, a->vm, false) &&
+ th_check_reg(s, a->rd, false) &&
+ th_check_reg(s, a->rs2, false) &&
+ (s->sew != 0);
+}
+
+#define GEN_OPFV_TRANS_TH(NAME, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (CHECK(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ gen_helper_##NAME##_d, \
+ }; \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ \
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
+ vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), tcg_env, \
+ s->cfg_ptr->vlenb, \
+ s->cfg_ptr->vlenb, data, \
+ fns[s->sew - 1]); \
+ finalize_rvv_inst(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFV_TRANS_TH(th_vfsqrt_v, opfv_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vfsqrt_v)
TH_TRANS_STUB(th_vfmin_vv)
TH_TRANS_STUB(th_vfmin_vf)
TH_TRANS_STUB(th_vfmax_vv)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index ac8e576c49..7274e7aedb 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -2942,3 +2942,44 @@ THCALL(TH_OPFVF3, th_vfwnmsac_vf_h, WOP_UUU_H, H4, H2,
fwnmsac16)
THCALL(TH_OPFVF3, th_vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
GEN_TH_VF(th_vfwnmsac_vf_h, 2, 4, clearl_th)
GEN_TH_VF(th_vfwnmsac_vf_w, 4, 8, clearq_th)
+
+/* Vector Floating-Point Square-Root Instruction */
+
+#define TH_OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
+static void do_##NAME(void *vd, void *vs2, int i, \
+ CPURISCVState *env) \
+{ \
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
+ *((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \
+}
+
+#define GEN_TH_V_ENV(NAME, ESZ, DSZ, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vlmax = th_maxsz(desc) / ESZ; \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ if (vl == 0) { \
+ return; \
+ } \
+ for (i = env->vstart; i < vl; i++) { \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ do_##NAME(vd, vs2, i, env); \
+ } \
+ env->vstart = 0; \
+ CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+}
+
+THCALL(TH_OPFVV1, th_vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
+THCALL(TH_OPFVV1, th_vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt)
+THCALL(TH_OPFVV1, th_vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt)
+GEN_TH_V_ENV(th_vfsqrt_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfsqrt_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfsqrt_v_d, 8, 8, clearq_th)
--
2.44.0
