On 4/14/21 12:11 PM, Richard Henderson wrote:
This approach seems like it will work fine for MLS and MMIR prefixes. For 8LS,
8RR, and MRR prefixes, we'll need some extra help within ppc_tr_translate_insn.
E.g.
insn = translator_ldl_swap(env, ctx->base.pc_next,
On 4/14/21 12:11 PM, Richard Henderson wrote:
static bool
allow_prefix_MLS(DisasContext *ctx, arg_D *a)
{
int64_t imm;
/* Require MLS prefix or no prefix. */
if (ctx->prefix_type != PREFIX_MLS) {
if (ctx->prefix_type == PREFIX_NONE) {
return true;
}
On 4/13/21 2:11 PM, Luis Pires wrote:
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -0,0 +1,26 @@
Missing copyright+license header.
+static bool trans_paddi(DisasContext *ctx, arg_paddi *a)
+{
+if (a->r == 0) {
+if (a->ra == 0) {
+/* li case */
+tcg_g
Hi Phil,
> > +
> > +%p_D8_SI32:s18 0:16
> > +
> > +# Fixed-Point Facility Instructions
> > +&addi r rt ra si
> > +
> > +paddi 01 10 0 -- r:1 -- .. 001110 rt:5 ra:5
> >
> si=%p_D8_SI &addi
>
> IIUC you should be able to do something like catch ra=0
Hi Luis,
On 4/13/21 11:11 PM, Luis Pires wrote:
> This implements the Power ISA 3.1 prefixed (64-bit) paddi
> instruction, while also replacing the legacy addi implementation.
> Both using the decode tree.
>
> Signed-off-by: Luis Pires
> Signed-off-by: Matheus Ferst
> ---
> target/ppc/ppc.deco
This implements the Power ISA 3.1 prefixed (64-bit) paddi
instruction, while also replacing the legacy addi implementation.
Both using the decode tree.
Signed-off-by: Luis Pires
Signed-off-by: Matheus Ferst
---
target/ppc/ppc.decode | 8 +++
target/ppc/translate.c
