The instruction has the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com>
---
target/riscv/helper.h | 5 ++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 27 ++++++++++++++++++-
target/riscv/xtheadvector_helper.c | 26 ++++++++++++++++++
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a1c85e5254..fe264621ff 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2311,3 +2311,8 @@ DEF_HELPER_5(th_viota_m_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(th_viota_m_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(th_viota_m_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(th_viota_m_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_4(th_vid_v_b, void, ptr, ptr, env, i32)
+DEF_HELPER_4(th_vid_v_h, void, ptr, ptr, env, i32)
+DEF_HELPER_4(th_vid_v_w, void, ptr, ptr, env, i32)
+DEF_HELPER_4(th_vid_v_d, void, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 93f4ee4a12..9a0ea606ab 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2562,13 +2562,38 @@ static bool trans_th_viota_m(DisasContext *s,
arg_th_viota_m *a)
return false;
}
+/* Vector Element Index Instruction */
+static bool trans_th_vid_v(DisasContext *s, arg_th_vid_v *a)
+{
+ if (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_reg(s, a->rd, false) &&
+ th_check_overlap_mask(s, a->rd, a->vm, false)) {
+ uint32_t data = 0;
+
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm);
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul);
+ static gen_helper_gvec_2_ptr * const fns[4] = {
+ gen_helper_th_vid_v_b, gen_helper_th_vid_v_h,
+ gen_helper_th_vid_v_w, gen_helper_th_vid_v_d,
+ };
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ tcg_env, s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb,
+ data, fns[s->sew]);
+ finalize_rvv_inst(s);
+ return true;
+ }
+ return false;
+}
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vid_v)
TH_TRANS_STUB(th_vext_x_v)
TH_TRANS_STUB(th_vmv_s_x)
TH_TRANS_STUB(th_vfmv_f_s)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index b0ddb3b307..0743d57b12 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3652,3 +3652,29 @@ GEN_TH_VIOTA_M(th_viota_m_b, uint8_t, H1, clearb_th)
GEN_TH_VIOTA_M(th_viota_m_h, uint16_t, H2, clearh_th)
GEN_TH_VIOTA_M(th_viota_m_w, uint32_t, H4, clearl_th)
GEN_TH_VIOTA_M(th_viota_m_d, uint64_t, H8, clearq_th)
+
+/* Vector Element Index Instruction */
+#define GEN_TH_VID_V(NAME, ETYPE, H, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vlmax = (env_archcpu(env)->cfg.vlenb << 3) / mlen; \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ int i; \
+ \
+ VSTART_CHECK_EARLY_EXIT(env); \
+ for (i = env->vstart; i < vl; i++) { \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + H(i)) = i; \
+ } \
+ env->vstart = 0; \
+ CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+}
+
+GEN_TH_VID_V(th_vid_v_b, uint8_t, H1, clearb_th)
+GEN_TH_VID_V(th_vid_v_h, uint16_t, H2, clearh_th)
+GEN_TH_VID_V(th_vid_v_w, uint32_t, H4, clearl_th)
+GEN_TH_VID_V(th_vid_v_d, uint64_t, H8, clearq_th)
--
2.44.0
