The instruction has the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com> --- target/riscv/helper.h | 5 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 36 ++++++++++++++++--- target/riscv/xtheadvector_helper.c | 27 ++++++++++++++ 3 files changed, 63 insertions(+), 5 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b650e299cf..b46f9fc2c3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -2342,3 +2342,8 @@ DEF_HELPER_6(th_vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(th_vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc index f6da1ff384..65b595d699 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -2898,10 +2898,36 @@ static bool trans_th_vrgather_vi(DisasContext *s, arg_rmrr *a) return true; } -#define TH_TRANS_STUB(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ -{ \ - return require_xtheadvector(s); \ +/* Vector Compress Instruction */ +static bool vcompress_vm_check_th(DisasContext *s, arg_r *a) +{ + return (require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_reg(s, a->rd, false) && + th_check_reg(s, a->rs2, false) && + th_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && + (a->rd != a->rs2)) && + s->vstart_eq_zero; } -TH_TRANS_STUB(th_vcompress_vm) +static bool trans_th_vcompress_vm(DisasContext *s, arg_r *a) +{ + if (vcompress_vm_check_th(s, a)) { + uint32_t data = 0; + static gen_helper_gvec_4_ptr * const fns[4] = { + gen_helper_th_vcompress_vm_b, gen_helper_th_vcompress_vm_h, + gen_helper_th_vcompress_vm_w, gen_helper_th_vcompress_vm_d, + }; + + data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), + tcg_env, s->cfg_ptr->vlenb, + s->cfg_ptr->vlenb, data, + fns[s->sew]); + finalize_rvv_inst(s); + return true; + } + return false; +} diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c index 2598824bb3..656f83f408 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -3865,3 +3865,30 @@ GEN_TH_VRGATHER_VX(th_vrgather_vx_b, uint8_t, H1, clearb_th) GEN_TH_VRGATHER_VX(th_vrgather_vx_h, uint16_t, H2, clearh_th) GEN_TH_VRGATHER_VX(th_vrgather_vx_w, uint32_t, H4, clearl_th) GEN_TH_VRGATHER_VX(th_vrgather_vx_d, uint64_t, H8, clearq_th) + +/* Vector Compress Instruction */ +#define GEN_TH_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vlmax = (env_archcpu(env)->cfg.vlenb << 3) / mlen; \ + uint32_t vl = env->vl; \ + uint32_t num = 0, i; \ + \ + for (i = env->vstart; i < vl; i++) { \ + if (!th_elem_mask(vs1, mlen, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ + num++; \ + } \ + env->vstart = 0; \ + CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +} + +/* Compress into vd elements of vs2 where vs1 is enabled */ +GEN_TH_VCOMPRESS_VM(th_vcompress_vm_b, uint8_t, H1, clearb_th) +GEN_TH_VCOMPRESS_VM(th_vcompress_vm_h, uint16_t, H2, clearh_th) +GEN_TH_VCOMPRESS_VM(th_vcompress_vm_w, uint32_t, H4, clearl_th) +GEN_TH_VCOMPRESS_VM(th_vcompress_vm_d, uint64_t, H8, clearq_th) -- 2.44.0