Signed-off-by: Víctor Colombo <victor.colo...@eldorado.org.br>
---
target/ppc/insn32.decode | 5 ++++
target/ppc/translate/fp-impl.c.inc | 41 ++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 8954a13d6b..da507758b8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -133,6 +133,9 @@
&X_imm2 rt imm
@X_imm2 ...... rt:5 ..... ... imm:2 .......... . &X_imm2
+&X_imm3 rt imm
+@X_imm3 ...... rt:5 ..... .. imm:3 .......... . &X_imm3
+
%x_xt 0:1 21:5
&X_imm5 xt imm:uint8_t vrb
@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5
xt=%x_xt
@@ -348,7 +351,9 @@ SETNBCR 011111 ..... ..... ----- 0111100000 -
@X_bi
MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
+MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
+MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3
MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
### Decimal Floating-Point Arithmetic Instructions
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index d6231358f8..319513d001 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -696,6 +696,27 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a)
return true;
}
+static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a)
+{
+ TCGv_i64 t1, fpscr;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
+
+ t1 = tcg_temp_new_i64();
+ get_fpr(t1, a->rb);
+ tcg_gen_andi_i64(t1, t1, FP_DRN);
+
+ gen_reset_fpstatus();
+ fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
+ store_fpscr_masked(fpscr, FP_DRN, t1, 0x0100);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(fpscr);
+
+ return true;
+}
+
static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a)
{
TCGv_i64 t1, fpscr;
@@ -716,6 +737,26 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2
*a)
return true;
}
+static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a)
+{
+ TCGv_i64 t1, fpscr;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_movi_i64(t1, (uint64_t)a->imm << FPSCR_DRN0);
+
+ gen_reset_fpstatus();
+ fpscr = place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN);
+ store_fpscr_masked(fpscr, FP_DRN, t1, 0x0100);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(fpscr);
+
+ return true;
+}
+
static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
{
TCGv_i64 fpscr;
--
2.25.1
