e, but fail to apply that
index properly across Zn and Zn+1.
r~
>
> -Original Message-
> From: Richard Henderson
> Sent: Friday, April 24, 2020 2:37 PM
> To: Stephen Long ; qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; Ana Pazos
> Subject: [EXT] Re: [PATCH RFC]
; qemu-devel@nongnu.org
Cc: qemu-...@nongnu.org; Ana Pazos
Subject: [EXT] Re: [PATCH RFC] target/arm: Implement SVE2 TBL, TBX
On 4/23/20 9:42 AM, Stephen Long wrote:
> Signed-off-by: Stephen Long
>
> These insns don't show up under any SVE2 categories in the manual. But
> if you
On 4/23/20 9:42 AM, Stephen Long wrote:
> Signed-off-by: Stephen Long
>
> These insns don't show up under any SVE2 categories in the manual. But
> if you lookup each insn, you'll find they have SVE2 variants.
> ---
> target/arm/helper-sve.h| 10 +++
> target/arm/sve.decode | 5
Signed-off-by: Stephen Long
These insns don't show up under any SVE2 categories in the manual. But
if you lookup each insn, you'll find they have SVE2 variants.
---
target/arm/helper-sve.h| 10 +++
target/arm/sve.decode | 5
target/arm/sve_helper.c| 53
