The presence of the Back-Invalidate (BI) decoder capability structure indicates a CXL downstream port, root port, or device supports the BI messages.
Add the BI capability structure to the accelerator device. Not-Yet-Signed-off-by: Ira Weiny <ira.we...@intel.com> --- hw/cxl/cxl-component-utils.c | 5 +++++ hw/mem/cxl_type3.c | 11 +++++++++++ include/hw/cxl/cxl_component.h | 11 +++++++++-- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 7949d12b7351..a9efa252b4ae 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -228,6 +228,7 @@ void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk init_cap_reg(EXTSEC, 6, 1); init_cap_reg(SNOOP, 8, 1); /* FALL THROUGH */ + case CXL3_TYPE2_DEVICE: case CXL2_UPSTREAM_PORT: case CXL2_TYPE3_DEVICE: case CXL2_LOGICAL_DEVICE: @@ -246,6 +247,10 @@ void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk abort(); } + if (type == CXL3_TYPE2_DEVICE) { + init_cap_reg(BI_DECODER, 12, 1); + } + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); #undef init_cap_reg } diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index c7eafd76d1ea..95fdaaa18f37 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1692,6 +1692,16 @@ static void ct3d_registers(void) type_init(ct3d_registers); +static void accel_reset(DeviceState *dev) +{ + CXLAccelDev *acceld = CXL_ACCEL(dev); + uint32_t *reg_state = acceld->parent_obj.cxl_cstate.crb.cache_mem_registers; + uint32_t *write_msk = acceld->parent_obj.cxl_cstate.crb.cache_mem_regs_write_mask; + + cxl_component_register_init_common(reg_state, write_msk, CXL3_TYPE2_DEVICE); + cxl_device_register_init_common(&acceld->parent_obj.cxl_dstate); +} + static void cxl_accel_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -1703,6 +1713,7 @@ static void cxl_accel_class_init(ObjectClass *oc, void *data) pc->revision = 1; dc->desc = "CXL Accelerator Device (Type 2)"; + dc->reset = accel_reset; } static const TypeInfo cxl_accel_dev_info = { diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 7c08c02c5e9d..a5b5512aed94 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -28,6 +28,7 @@ enum reg_type { CXL2_UPSTREAM_PORT, CXL2_DOWNSTREAM_PORT, CXL3_SWITCH_MAILBOX_CCI, + CXL3_TYPE2_DEVICE, }; /* @@ -66,6 +67,7 @@ CXLx_CAPABILITY_HEADER(LINK, 2) CXLx_CAPABILITY_HEADER(HDM, 3) CXLx_CAPABILITY_HEADER(EXTSEC, 4) CXLx_CAPABILITY_HEADER(SNOOP, 5) +CXLx_CAPABILITY_HEADER(BI_DECODER, 6) /* * Capability structures contain the actual registers that the CXL component @@ -185,9 +187,14 @@ HDM_DECODER_INIT(3); (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) #define CXL_SNOOP_REGISTERS_SIZE 0x8 +/* CXL 3.0 8.2.4.26 - CXL BI Decoder Capability Structure */ +#define CXL_BI_DECODER_REGISTERS_OFFSET \ + (CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) +#define CXL_BI_DECODER_REGISTERS_SIZE 0xC + /* CXL 3.0 8.2.3 Table 8-21 */ -QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + - CXL_SNOOP_REGISTERS_SIZE) >= CXL2_COMPONENT_CM_REGION_SIZE, +QEMU_BUILD_BUG_MSG((CXL_BI_DECODER_REGISTERS_OFFSET + + CXL_BI_DECODER_REGISTERS_SIZE) >= CXL2_COMPONENT_CM_REGION_SIZE, "No space for registers"); typedef struct component_registers { -- 2.40.0