Re: [PATCH for-4.2 1/2] i386: Add new versions of Skylake/Cascadelake/Icelake without TSX

2019-11-21 Thread Kashyap Chamarthy
On Wed, Nov 20, 2019 at 01:49:11PM -0300, Eduardo Habkost wrote: > One of the mitigation methods for TAA[1] is to disable TSX > support on the host system. Linux added a mechanism to disable > TSX globally through the kernel command line, and many Linux > distributions now default to tsx=off. Thi

Re: [PATCH for-4.2 1/2] i386: Add new versions of Skylake/Cascadelake/Icelake without TSX

2019-11-21 Thread Paolo Bonzini
On 20/11/19 19:42, Eduardo Habkost wrote: > The plan is to set default_cpu_version=CPU_VERSION_LATEST on > pc-*-5.0 (or, more likely, 5.1). But this will happen only after > libvirt starts resolving CPU model versions. See the > "Runnability guarantee of CPU models" section at > qemu-deprecated.t

Re: [PATCH for-4.2 1/2] i386: Add new versions of Skylake/Cascadelake/Icelake without TSX

2019-11-20 Thread Eduardo Habkost
On Wed, Nov 20, 2019 at 06:40:06PM +0100, Paolo Bonzini wrote: > On 20/11/19 17:49, Eduardo Habkost wrote: > > One of the mitigation methods for TAA[1] is to disable TSX > > support on the host system. Linux added a mechanism to disable > > TSX globally through the kernel command line, and many Li

Re: [PATCH for-4.2 1/2] i386: Add new versions of Skylake/Cascadelake/Icelake without TSX

2019-11-20 Thread Paolo Bonzini
On 20/11/19 17:49, Eduardo Habkost wrote: > One of the mitigation methods for TAA[1] is to disable TSX > support on the host system. Linux added a mechanism to disable > TSX globally through the kernel command line, and many Linux > distributions now default to tsx=off. This makes existing CPU >

[PATCH for-4.2 1/2] i386: Add new versions of Skylake/Cascadelake/Icelake without TSX

2019-11-20 Thread Eduardo Habkost
One of the mitigation methods for TAA[1] is to disable TSX support on the host system. Linux added a mechanism to disable TSX globally through the kernel command line, and many Linux distributions now default to tsx=off. This makes existing CPU models that have HLE and RTM enabled not usable anym