riscv_cpu_validate_v() consists of checking RVV related attributes, such as vlen and elen, and setting env->vext_spec.
This can be done during riscv_cpu_validate_misa_ext() time, allowing us to fail earlier if RVV constrains are not met. Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fa1954a850..0d8524d0d9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1027,6 +1027,9 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) { + CPURISCVState *env = &cpu->env; + Error *local_err = NULL; + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); @@ -1073,6 +1076,12 @@ static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) error_setg(errp, "V extension requires D and F extensions"); return; } + + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } } } @@ -1111,7 +1120,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env = &cpu->env; - Error *local_err = NULL; uint32_t ext = 0; if (cpu->cfg.epmp && !cpu->cfg.pmp) { @@ -1202,14 +1210,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } - if (cpu->cfg.ext_v) { - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - } - if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; -- 2.39.2