Hi,
This is a re-send of the patch sent as a 9.0 bugfix in [1], now reframed
as a non-bug fix chabge,
A new patch (2) was added to handle a similar scenario with ebreak and tval.
Changes from v1:
- patch 1:
- rewrite commit msg to make it clear that this is a non-bug
fix change
- new patch (2):
- set mtval/stval during ebreak
- v1 link:
https://lore.kernel.org/qemu-riscv/20240320093221.220854-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (2):
target/riscv/debug: set tval=pc in breakpoint exceptions
trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
target/riscv/cpu_helper.c | 1 +
target/riscv/debug.c | 3 +++
target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++
3 files changed, 8 insertions(+)
--
2.44.0
