Re: [PATCH for-9.2 v6 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

2024-08-27 Thread Daniel Henrique Barboza
On 8/26/24 11:44 PM, Tomasz Jeznach wrote: On Fri, Aug 23, 2024 at 10:18 AM Daniel Henrique Barboza wrote: On 8/20/24 12:27 PM, Jason Chien wrote: Hi Daniel, On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can us

Re: [PATCH for-9.2 v6 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

2024-08-26 Thread Tomasz Jeznach
On Fri, Aug 23, 2024 at 10:18 AM Daniel Henrique Barboza wrote: > > > > On 8/20/24 12:27 PM, Jason Chien wrote: > > Hi Daniel, > > > > On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote: > >> From: Tomasz Jeznach > >> > >> The RISC-V IOMMU spec predicts that the IOMMU can use translation caches

Re: [PATCH for-9.2 v6 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

2024-08-23 Thread Daniel Henrique Barboza
On 8/20/24 12:27 PM, Jason Chien wrote: Hi Daniel, On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are m

Re: [PATCH for-9.2 v6 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

2024-08-20 Thread Jason Chien
Hi Daniel, On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some

[PATCH for-9.2 v6 08/12] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

2024-08-01 Thread Daniel Henrique Barboza
From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some artifacts included in the cache that predicts s-stage and g-stage e