Re: [PATCH qemu] target/riscv: rvv: Fix early exit condition for whole register load/store

2022-05-09 Thread Alistair Francis
On Fri, May 6, 2022 at 7:17 AM ~eopxd wrote: > > From: eopXD > > Vector whole register load instructions have EEW encoded in the opcode, > so we shouldn't take SEW here. Vector whole register store instructions > are always EEW=8. > > Signed-off-by: eop Chen > Reviewed-by: Frank Chang Thanks!

Re: [PATCH qemu] target/riscv: rvv: Fix early exit condition for whole register load/store

2022-05-09 Thread Alistair Francis
On Fri, May 6, 2022 at 7:17 AM ~eopxd wrote: > > From: eopXD > > Vector whole register load instructions have EEW encoded in the opcode, > so we shouldn't take SEW here. Vector whole register store instructions > are always EEW=8. > > Signed-off-by: eop Chen > Reviewed-by: Frank Chang Acked-by

[PATCH qemu] target/riscv: rvv: Fix early exit condition for whole register load/store

2022-05-05 Thread ~eopxd
From: eopXD Vector whole register load instructions have EEW encoded in the opcode, so we shouldn't take SEW here. Vector whole register store instructions are always EEW=8. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 58 +