Re: [PATCH qemu v3 00/20] Fix malfunctioning of T2-T5 timers on the STM32 platform

2023-12-05 Thread Alistair Francis
On Sat, Dec 2, 2023 at 11:40 PM ~lbryndza wrote: > > Current implementation of T2 - T5 times on the STM32 platform does not > work properly. > After configuring the timer-counter circuit to report interrupts every > 10ms, in reality the first interrupt is reported > only once after a few seconds,

[PATCH qemu v3 00/20] Fix malfunctioning of T2-T5 timers on the STM32 platform

2023-12-02 Thread ~lbryndza
Current implementation of T2 - T5 times on the STM32 platform does not work properly. After configuring the timer-counter circuit to report interrupts every 10ms, in reality the first interrupt is reported only once after a few seconds, while subsequent interrupts do not come. The current code also