Re: [PATCH qemu v9 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

> Weiwei Li 於 2022年4月27日 下午7:55 寫道： > > > 在 2022/3/7 下午3:10, ~eopxd 写道: >> From: eopXD >> >> Destination register of unit-stride mask load and store instructions are >> always written with a tail-agnostic policy. >> >> Signed-off-by: eop Chen >> Reviewed-by: Frank Chang >> --- >> target/r

Re: [PATCH qemu v9 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

在 2022/3/7 下午3:10, ~eopxd 写道: From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 ++ target/riscv/vecto

[PATCH qemu v9 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 11 ++ target/riscv/vector_helper.c| 28 +