We use cap_frozen to mark cap/ecap read/writable or read-only,
At init stage, we allow to update cap/ecap based on host IOMMU
cap/ecap, but when machine create done, cap_frozen is set and
we only allow checking cap/ecap for compatibility.
Currently only stage-2 translation is supported which is backed by
shadow page table on host side. So we don't need exact matching of
each bit of cap/ecap between vIOMMU and host. However, we can still
ensure compatibility of host and vIOMMU's address width at least,
i.e., vIOMMU's mgaw <= host IOMMU mgaw, which is missed before.
When stage-1 translation is supported in future, a.k.a. scalable
modern mode, this mechanism will be further extended to check more
bits.
Signed-off-by: Yi Liu <yi.l....@intel.com>
Signed-off-by: Yi Sun <yi.y....@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
---
hw/i386/intel_iommu_internal.h | 1 +
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 29 +++++++++++++++++++++++++++++
3 files changed, 31 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 3301f54b35..33d2298dce 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -206,6 +206,7 @@
#define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
#define VTD_CAP_ND (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
#define VTD_ADDRESS_SIZE(aw) (1ULL << (aw))
+#define VTD_CAP_MGAW_MASK (0x3fULL << 16)
#define VTD_CAP_MGAW(aw) ((((aw) - 1) & 0x3fULL) << 16)
#define VTD_MAMV 18ULL
#define VTD_CAP_MAMV (VTD_MAMV << 48)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index c71a133820..a0b530ebc6 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -47,6 +47,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState,
INTEL_IOMMU_DEVICE)
#define VTD_HOST_AW_48BIT 48
#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
+#define VTD_MGAW_FROM_CAP(cap) (((cap >> 16) & 0x3fULL) + 1)
#define DMAR_REPORT_F_INTR (1)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 7ed2b79669..409f8a59c3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -35,6 +35,7 @@
#include "sysemu/kvm.h"
#include "sysemu/dma.h"
#include "sysemu/sysemu.h"
+#include "sysemu/iommufd.h"
#include "hw/i386/apic_internal.h"
#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
@@ -3830,6 +3831,34 @@ static int vtd_check_iommufd_hdev(IntelIOMMUState *s,
IOMMUFDDevice *idev,
Error **errp)
{
+ struct iommu_hw_info_vtd vtd;
+ enum iommu_hw_info_type type = IOMMU_HW_INFO_TYPE_INTEL_VTD;
+ long host_mgaw, viommu_mgaw = VTD_MGAW_FROM_CAP(s->cap);
+ uint64_t tmp_cap = s->cap;
+ int ret;
+
+ ret = iommufd_device_get_info(idev, &type, sizeof(vtd), &vtd, errp);
+ if (ret) {
+ return ret;
+ }
+
+ if (type != IOMMU_HW_INFO_TYPE_INTEL_VTD) {
+ error_setg(errp, "IOMMU hardware is not compatible");
+ return -EINVAL;
+ }
+
+ host_mgaw = VTD_MGAW_FROM_CAP(vtd.cap_reg);
+ if (viommu_mgaw > host_mgaw) {
+ if (s->cap_frozen) {
+ error_setg(errp, "mgaw %" PRId64 " > host mgaw %" PRId64,
+ viommu_mgaw, host_mgaw);
+ return -EINVAL;
+ }
+ tmp_cap &= ~VTD_CAP_MGAW_MASK;
+ tmp_cap |= VTD_CAP_MGAW(host_mgaw + 1);
+ }
+
+ s->cap = tmp_cap;
return 0;
}
--
2.34.1
