Hi,
This series adds LoongArch LASX instructions.
About test:
We use RISU test the LoongArch LASX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lasx
RISU:
https://github.com/loongson/risu/tree/loongarch-suport-lasx
Please review, Thanks.
Song Gao (46):
target/loongarch: Add LASX data type XReg
target/loongarch: meson.build support build LASX
target/loongarch: Add CHECK_ASXE maccro for check LASX enable
target/loongarch: Implement xvadd/xvsub
target/loongarch: Implement xvreplgr2vr
target/loongarch: Implement xvaddi/xvsubi
target/loongarch: Implement xvneg
target/loongarch: Implement xvsadd/xvssub
target/loongarch: Implement xvhaddw/xvhsubw
target/loongarch: Implement xvaddw/xvsubw
target/loongarch: Implement xavg/xvagr
target/loongarch: Implement xvabsd
target/loongarch: Implement xvadda
target/loongarch: Implement xvmax/xvmin
target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
target/loongarch; Implement xvdiv/xvmod
target/loongarch: Implement xvsat
target/loongarch: Implement xvexth
target/loongarch: Implement vext2xv
target/loongarch: Implement xvsigncov
target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz
target/loognarch: Implement xvldi
target/loongarch: Implement LASX logic instructions
target/loongarch: Implement xvsll xvsrl xvsra xvrotr
target/loongarch: Implement xvsllwil xvextl
target/loongarch: Implement xvsrlr xvsrar
target/loongarch: Implement xvsrln xvsran
target/loongarch: Implement xvsrlrn xvsrarn
target/loongarch: Implement xvssrln xvssran
target/loongarch: Implement xvssrlrn xvssrarn
target/loongarch: Implement xvclo xvclz
target/loongarch: Implement xvpcnt
target/loongarch: Implement xvbitclr xvbitset xvbitrev
target/loongarch: Implement xvfrstp
target/loongarch: Implement LASX fpu arith instructions
target/loongarch: Implement LASX fpu fcvt instructions
target/loongarch: Implement xvseq xvsle xvslt
target/loongarch: Implement xvfcmp
target/loongarch: Implement xvbitsel xvset
target/loongarch: Implement xvinsgr2vr xvpickve2gr
target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v
target/loongarch: Implement xvpack xvpick xvilv{l/h}
target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins
target/loongarch: Implement xvld xvst
target/loongarch: CPUCFG support LASX
linux-user/loongarch64/signal.c | 1 +
target/loongarch/cpu.c | 4 +
target/loongarch/cpu.h | 16 +
target/loongarch/disas.c | 924 +++++
target/loongarch/gdbstub.c | 1 +
target/loongarch/helper.h | 592 ++++
target/loongarch/insn_trans/trans_lasx.c.inc | 3203 +++++++++++++++++
target/loongarch/insns.decode | 828 +++++
target/loongarch/internals.h | 22 -
target/loongarch/lasx_helper.c | 3221 ++++++++++++++++++
target/loongarch/lsx_helper.c | 111 +-
target/loongarch/machine.c | 40 +-
target/loongarch/meson.build | 1 +
target/loongarch/translate.c | 18 +
target/loongarch/vec.h | 125 +
15 files changed, 9006 insertions(+), 101 deletions(-)
create mode 100644 target/loongarch/insn_trans/trans_lasx.c.inc
create mode 100644 target/loongarch/lasx_helper.c
create mode 100644 target/loongarch/vec.h
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2.39.1
