On Thu, Jan 2, 2020 at 10:18 AM Palmer Dabbelt wrote:
>
> On Mon, 09 Dec 2019 10:10:43 PST (-0800), Alistair Francis wrote:
> > The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
> > Now that we don't use atomics for MIP we can change this back to a xlen
> > CSR.
> >
> > Signed
On Mon, 09 Dec 2019 10:10:43 PST (-0800), Alistair Francis wrote:
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --g