On Mon, 09 Dec 2019 10:10:50 PST (-0800), Alistair Francis wrote:
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 21 +
target/riscv/
Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 21 +
target/riscv/cpu_bits.h | 34 +-
target/riscv/gdb
