Re: [PATCH v1 1/1] target/riscv: Correctly implement TSR trap

2020-03-05 Thread Palmer Dabbelt
On Thu, 20 Feb 2020 10:41:35 PST (-0800), alistai...@gmail.com wrote: On Mon, Jan 20, 2020 at 9:43 PM Alistair Francis wrote: As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privle

Re: [PATCH v1 1/1] target/riscv: Correctly implement TSR trap

2020-02-20 Thread Alistair Francis
On Mon, Jan 20, 2020 at 9:43 PM Alistair Francis wrote: > > As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't > correctly handling illegal instructions based on the value of MSTATUS_TSR > and the current privledge level. > > This patch fixes the issue raised in the bug by rai

Re: [PATCH v1 1/1] target/riscv: Correctly implement TSR trap

2020-01-21 Thread Jonathan Behrens
Looks good to me. Though this is I think the third bug in privilege checking in op_helper.c which is only like 150 lines long total. It would be really good to fully double check that there aren't any more lurking there... Reviewed-by: Jonathan Behrens > On Tue, Jan 21, 2020 at 12:45 AM Alistair

[PATCH v1 1/1] target/riscv: Correctly implement TSR trap

2020-01-20 Thread Alistair Francis
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Sig