Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-11-01 Thread Palmer Dabbelt
On Tue, 29 Oct 2019 23:54:30 PDT (-0700), alistai...@gmail.com wrote: On Tue, Oct 29, 2019 at 4:14 PM Palmer Dabbelt wrote: On Tue, 29 Oct 2019 03:49:23 PDT (-0700), alistai...@gmail.com wrote: > On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis wrote: >> >> On Fri, Oct 18, 2019 at 9:51 AM Pal

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-29 Thread Alistair Francis
On Tue, Oct 29, 2019 at 4:14 PM Palmer Dabbelt wrote: > > On Tue, 29 Oct 2019 03:49:23 PDT (-0700), alistai...@gmail.com wrote: > > On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis > > wrote: > >> > >> On Fri, Oct 18, 2019 at 9:51 AM Palmer Dabbelt wrote: > >> > > >> > On Tue, 08 Oct 2019 15:04

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-29 Thread Palmer Dabbelt
On Tue, 29 Oct 2019 03:49:23 PDT (-0700), alistai...@gmail.com wrote: On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis wrote: On Fri, Oct 18, 2019 at 9:51 AM Palmer Dabbelt wrote: > > On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote: > > Instead of relying on atomics to access

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-29 Thread Alex Bennée
Alistair Francis writes: > Instead of relying on atomics to access the MIP register let's update > our helper function to instead just lock the IO mutex thread before > writing. This follows the same concept as used in PPC for handling > interrupts > > Signed-off-by: Alistair Francis Acked-by

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-29 Thread Alistair Francis
On Fri, Oct 18, 2019 at 7:44 PM Alistair Francis wrote: > > On Fri, Oct 18, 2019 at 9:51 AM Palmer Dabbelt wrote: > > > > On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote: > > > Instead of relying on atomics to access the MIP register let's update > > > our helper function to inst

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-18 Thread Alistair Francis
On Fri, Oct 18, 2019 at 9:51 AM Palmer Dabbelt wrote: > > On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote: > > Instead of relying on atomics to access the MIP register let's update > > our helper function to instead just lock the IO mutex thread before > > writing. This follows th

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-18 Thread Palmer Dabbelt
On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote: Instead of relying on atomics to access the MIP register let's update our helper function to instead just lock the IO mutex thread before writing. This follows the same concept as used in PPC for handling interrupts Signed-off-by:

Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-08 Thread Richard Henderson
On 10/8/19 6:04 PM, Alistair Francis wrote: > Instead of relying on atomics to access the MIP register let's update > our helper function to instead just lock the IO mutex thread before > writing. This follows the same concept as used in PPC for handling > interrupts > > Signed-off-by: Alistair Fr

[PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR

2019-10-08 Thread Alistair Francis
Instead of relying on atomics to access the MIP register let's update our helper function to instead just lock the IO mutex thread before writing. This follows the same concept as used in PPC for handling interrupts Signed-off-by: Alistair Francis --- target/riscv/cpu.c| 5 ++-- target/