Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension

2020-01-21 Thread Anup Patel
On Tue, Jan 21, 2020 at 4:43 PM Alistair Francis wrote: > > On Wed, Jan 8, 2020 at 12:07 PM Palmer Dabbelt > wrote: > > > > On Mon, 09 Dec 2019 10:11:24 PST (-0800), Alistair Francis wrote: > > > Signed-off-by: Alistair Francis > > > --- > > > target/riscv/csr.c | 3 +++ > > > 1 file changed,

Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension

2020-01-21 Thread Alistair Francis
On Wed, Jan 8, 2020 at 12:07 PM Palmer Dabbelt wrote: > > On Mon, 09 Dec 2019 10:11:24 PST (-0800), Alistair Francis wrote: > > Signed-off-by: Alistair Francis > > --- > > target/riscv/csr.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c

Re: [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension

2020-01-07 Thread Palmer Dabbelt
On Mon, 09 Dec 2019 10:11:24 PST (-0800), Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a4b598d49a..fc38c45a7e 100644 --- a/target/riscv/csr.c +++ b/target/riscv

[PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension

2019-12-09 Thread Alistair Francis
Signed-off-by: Alistair Francis --- target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a4b598d49a..fc38c45a7e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -449,6 +449,9 @@ static int read_mideleg(CPURISCVState *en