Re: [PATCH v1 2/2] hw/net:ftgmac100: support 64 bits dma dram address for AST2700

2024-06-21 Thread Cédric Le Goater
On 6/19/24 12:01 PM, Jamin Lin wrote: ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "Normal Priority Transmit Ring Base Address Register High(0x17C)", "High Priority Transmit Ring Base Address Register

[PATCH v1 2/2] hw/net:ftgmac100: support 64 bits dma dram address for AST2700

2024-06-19 Thread Jamin Lin via
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "Normal Priority Transmit Ring Base Address Register High(0x17C)", "High Priority Transmit Ring Base Address Register High(0x184)" and "Receive Ring Base Addr