Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-17 Thread gaosong
Hi Richard, On 2021/11/17 下午5:55, Richard Henderson wrote: @fmt_rr_i12 and @fmt_rr_ui12 are two 'Formats',  but they use the same 'Argument sets'(rr_i). What I meant is that there would be a single gen_rr_i function handing the argument set rr_i; no need for two gen_rr_i* functions. Got

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-17 Thread Richard Henderson
On 11/17/21 10:29 AM, gaosong wrote: gen_rr_i ? The code is not written completely, like this: gen_rr_i12: @fmt_rr_i12   .. imm:s12 rj:5 rd:5 _i slti 001000 . . @fmt_rr_i12 sltui 001001 . .

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-17 Thread gaosong
Hi Richard, On 2021/11/17 下午4:28, Richard Henderson wrote: On 11/17/21 8:57 AM, gaosong wrote: I see that  insns.decode format is not very consistent with other architectures, such ARM/RISCV No.  I don't like how riscv has done it, though they have quite a few split fields, so perhaps they

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-17 Thread Richard Henderson
On 11/17/21 8:57 AM, gaosong wrote: I see that  insns.decode format is not very consistent with other architectures, such ARM/RISCV No. I don't like how riscv has done it, though they have quite a few split fields, so perhaps they thought it looked weird. # # Argument sets # _i 

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-17 Thread gaosong
Hi Richard, On 2021/11/15 下午4:42, Richard Henderson wrote: On 11/15/21 4:59 AM, gaosong wrote: 'The width of the immediate is a detail of the format'  means: _rdrjimm rd  rj imm @fmt_rdrjimm .. imm:12  rj:5 rd:5 _rdrjimm @fmt_rdrjimm14 imm:14  rj:5

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-15 Thread Richard Henderson
On 11/15/21 4:59 AM, gaosong wrote: 'The width of the immediate is a detail of the format' means: _rdrjimm rd rj imm @fmt_rdrjimm .. imm:12 rj:5 rd:5 _rdrjimm @fmt_rdrjimm14 imm:14 rj:5 rd:5 _rdrjimm @fmt_rdrjimm16 .. imm:16

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-14 Thread gaosong
Hi Richard, On 2021/11/12 下午10:05, Richard Henderson wrote: On 11/12/21 7:53 AM, Song Gao wrote: +# +# Fields +# +%rd  0:5 +%rj  5:5 +%rk  10:5 +%sa2 15:2 +%si12    10:s12 +%ui12    10:12 +%si16    10:s16 +%si20    5:s20 You should only create separate field definitions like

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-12 Thread WANG Xuerui
On 11/12/21 22:05, Richard Henderson wrote: On 11/12/21 7:53 AM, Song Gao wrote: +# +# Fields +# +%rd  0:5 +%rj  5:5 +%rk  10:5 +%sa2 15:2 +%si12    10:s12 +%ui12    10:12 +%si16    10:s16 +%si20    5:s20 You should only create separate field definitions like this when they

Re: [PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-12 Thread Richard Henderson
On 11/12/21 7:53 AM, Song Gao wrote: +# +# Fields +# +%rd 0:5 +%rj 5:5 +%rk 10:5 +%sa2 15:2 +%si1210:s12 +%ui1210:12 +%si1610:s16 +%si205:s20 You should only create separate field definitions like this when they are complex: e.g. the logical field is

[PATCH v10 04/26] target/loongarch: Add fixed point arithmetic instruction translation

2021-11-11 Thread Song Gao
This includes: - ADD.{W/D}, SUB.{W/D} - ADDI.{W/D}, ADDU16ID - ALSL.{W[U]/D} - LU12I.W, LU32I.D LU52I.D - SLT[U], SLT[U]I - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I - AND, OR, NOR, XOR, ANDN, ORN - MUL.{W/D}, MULH.{W[U]/D[U]} - MULW.D.W[U] - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]} - ANDI, ORI, XORI