Re: [PATCH v10 06/61] target/riscv: add vector stride load and store instructions

On 2020/6/24 0:52, Alistair Francis wrote: On Fri, Jun 19, 2020 at 9:49 PM LIU Zhiwei wrote: Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified

Re: [PATCH v10 06/61] target/riscv: add vector stride load and store instructions

On Fri, Jun 19, 2020 at 9:49 PM LIU Zhiwei wrote: > > Vector strided operations access the first memory element at the base address, > and then access subsequent elements at address increments given by the byte > offset contained in the x register specified by rs2. > > Vector unit-stride operation

[PATCH v10 06/61] target/riscv: add vector stride load and store instructions

Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from

[PATCH v10 06/61] target/riscv: add vector stride load and store instructions

Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from