Hi Tejus,
(Also +Paolo/Daniel)
On Tue, Apr 30, 2024 at 06:14:52AM +, Tejus GK wrote:
> Date: Tue, 30 Apr 2024 06:14:52 +
> From: Tejus GK
> Subject: Re: [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo
>
>
>
> On 24 Apr 2024, at 9:1
On 24 Apr 2024, at 9:19 PM, Zhao Liu wrote:
@@ -2140,6 +2164,7 @@ static const CPUCaches epyc_milan_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
+.share_level = CPU_TOPO_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated with a specific cpu topolo
