Re: [PATCH v11 3/5] target/riscv: generate virtual instruction exception

On Sun, Oct 16, 2022 at 10:58 PM Mayuresh Chitale wrote: > > This patch adds a mechanism to generate a virtual instruction > instruction exception instead of an illegal instruction exception > during instruction decode when virt is enabled. > > Signed-off-by: Mayuresh Chitale Reviewed-by:

Re: [PATCH v11 3/5] target/riscv: generate virtual instruction exception

On 2022/10/16 20:47, Mayuresh Chitale wrote: This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale --- target/riscv/translate.c | 8

[PATCH v11 3/5] target/riscv: generate virtual instruction exception

This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale --- target/riscv/translate.c | 8 +++- 1 file changed, 7 insertions(+), 1