Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-12-14 Thread Alexander Duyck
Okay. That sounds reasonable. You should repost this with your more thorough explanation of the problem and how this solves it in the patch description. Thanks. - Alex On Mon, Dec 14, 2020 at 3:09 AM Andrew Melnichenko wrote: > > Hi, > The issue is in LSC clearing. So, after "link up"(during in

Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-12-14 Thread Andrew Melnichenko
Hi, The issue is in LSC clearing. So, after "link up"(during initialization), the next LSC event is masked and can't be processed. Technically, the event should be 'cleared' during ICR read. On Windows guest, everything works well, mostly because of different interrupt routines(ICR clears during re

Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-12-03 Thread Alexander Duyck
On Thu, Dec 3, 2020 at 5:00 AM Andrew Melnychenko wrote: > > Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441 So the bugzilla seems to be reporting that the NIC operstate is being misreported when qemu has configured the link down. Based on the description it isn't clear to me how thi

[PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-12-03 Thread Andrew Melnychenko
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441 Added ICR clearing if there is IMS bit - according to the note by section 13.3.27 of the 8257X developers manual. Signed-off-by: Andrew Melnychenko --- hw/net/e1000e_core.c | 10 ++ hw/net/trace-events | 1 + 2 files changed,

Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-05-11 Thread Jason Wang
On 2020/5/11 下午6:08, Andrew Melnichenko wrote: Yo, So I think we should implement the 82574l behavior?  Well, as I understand it - its already implemented. I've added ICR clearance if ICR & IMS(also need to add ICR_ASSERTED check, my bad, I'll prepare new patch). Yes, but it behave m

Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-05-11 Thread Andrew Melnichenko
Yo, > So I think we should implement the 82574l behavior? Well, as I understand it - its already implemented. I've added ICR clearance if ICR & IMS(also need to add ICR_ASSERTED check, my bad, I'll prepare new patch). At first, I had hacks to clear 'msi_causes_pending' at 'e1000e_core_set_link_

Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-05-08 Thread Jason Wang
On 2020/5/9 上午2:13, Andrew Melnichenko wrote: Yo, I've used OpenSDM_8257x-18.pdf specification. This document was recommended by Intel guys(Also, they referenced to that note). I've made a fast fix and it works. Before that I had a fix for Linux e1000e driver. Overall, the issue was in pendin

Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-05-08 Thread Andrew Melnichenko
Yo, I've used OpenSDM_8257x-18.pdf specification. This document was recommended by Intel guys(Also, they referenced to that note). I've made a fast fix and it works. Before that I had a fix for Linux e1000e driver. Overall, the issue was in pending interrupts that can't be cleared by reading ICR in

Re: [PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-05-07 Thread Jason Wang
On 2020/5/7 上午5:26, and...@daynix.com wrote: From: Andrew Melnychenko Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441 Added ICR clearing if there is IMS bit - according to the note by section 13.3.27 of the 8257X developers manual. Signed-off-by: Andrew Melnychenko --- hw/net

[PATCH v2] e1000e: Added ICR clearing by corresponding IMS bit.

2020-05-06 Thread andrew
From: Andrew Melnychenko Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441 Added ICR clearing if there is IMS bit - according to the note by section 13.3.27 of the 8257X developers manual. Signed-off-by: Andrew Melnychenko --- hw/net/e1000e_core.c | 9 + hw/net/trace-events