Re: [PATCH v2] target/riscv: Add proper two-stage lookup exception detection

2021-03-22 Thread Alistair Francis
On Fri, Mar 19, 2021 at 10:16 AM Georg Kotheimer wrote: > > The current two-stage lookup detection in riscv_cpu_do_interrupt falls > short of its purpose, as all it checks is whether two-stage address > translation either via the hypervisor-load store instructions or the > MPRV feature would be

Re: [PATCH v2] target/riscv: Add proper two-stage lookup exception detection

2021-03-19 Thread Alistair Francis
On Fri, Mar 19, 2021 at 10:16 AM Georg Kotheimer wrote: > > The current two-stage lookup detection in riscv_cpu_do_interrupt falls > short of its purpose, as all it checks is whether two-stage address > translation either via the hypervisor-load store instructions or the > MPRV feature would be

[PATCH v2] target/riscv: Add proper two-stage lookup exception detection

2021-03-19 Thread Georg Kotheimer
The current two-stage lookup detection in riscv_cpu_do_interrupt falls short of its purpose, as all it checks is whether two-stage address translation either via the hypervisor-load store instructions or the MPRV feature would be allowed. What we really need instead is whether two-stage address