subject:"\[PATCH v2 0\/5\] hw\/riscv\: sifive_u\: Add Mode Select \(MSEL\[3\:0\]\) support"

Re: [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support

2020-06-16 Thread Alistair Francis

On Mon, Jun 15, 2020 at 5:51 PM Bin Meng wrote: > > From: Bin Meng > > This series updates the 'sifive_u' machine support: > > - Change SiFive E/U series CPU reset vector to 0x1004 > - Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new > "msel" machine property > - Add a dummy DDR mem

[PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support

2020-06-15 Thread Bin Meng

From: Bin Meng This series updates the 'sifive_u' machine support: - Change SiFive E/U series CPU reset vector to 0x1004 - Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new "msel" machine property - Add a dummy DDR memory controller device With this series, QEMU can boot U-Boot SPL